About the Project

About ATOMiK

Building state-aware compute from mathematical proof work to live prototype hardware.

The Mission

Many systems still spend too much work storing, moving, and rediscovering state. ATOMiK explores a different model. Delta-state algebra reconstructs state from deltas: small, commutative, self-inverse operations that compose in any order to produce the same result.

This is a state-aware compute primitive, not a general replacement for every storage or synchronization system. The math has formal proof work. The hardware has prototype-validation artifacts across FPGA paths. The software packages are available (pip install atomik-core).

The goal is to make delta-state algebra available at every layer of the stack — from a Python import to a custom ASIC — so that any engineer can stop moving data and start evolving it.

The Invention

From mathematical insight to evidence-labeled prototype hardware.

01

The Math

Delta-state algebra is modeled around Abelian-group properties under XOR.

02

The Proofs

Commutativity, associativity, self-inverse, and identity properties are represented in formal proof work.

03

The Software

Python and C SDK paths support pipeline orchestration, delta generators, and evaluation workflows.

04

The Silicon

FPGA prototype paths and synthesis-characterized scaling are documented. ASIC evaluation is roadmap work.

Technology Timeline

Every milestone built on the one before it.

2025

Mathematical Formalization

Formal proof work around Abelian-group properties: commutativity, associativity, self-inverse, and identity.

2025

Software SDK

Python and C libraries for pipeline orchestration, delta generation, and evaluation workflows.

2025

FPGA v1 -- PicoRV32 + ATOMiK

First silicon proof: ATOMiK core integrated with PicoRV32 RISC-V on a Tang Nano 9K. Repeat clock and throughput figures only from the linked hardware-validation artifacts.

2025

FPGA v2 -- Custom RV64I CPU

Built a custom 64-bit RISC-V CPU with native ATOMiK ISA extensions. Delta operations became first-class instructions, not MMIO.

2025

FPGA v3 -- HD Video + Multi-Node

FPGA display and multi-node prototype work. Use the hardware proof map for exact artifact labels before repeating any performance or board claims.

2026

Zynq Characterization

Synthesis-characterized Xilinx Zynq XC7Z020 scaling path with single-bank and parallel-bank resource notes. Use the hardware proof map for claim labels.

2026

Developer Evaluation Path

Public software and request-based evaluation materials make the architecture inspectable before any commercial commitment.

2026

ASIC Path Initiated

Sky130 and ASIC exploration are roadmap work until backed by publishable tape-out or silicon artifacts.

By the Numbers

FORMAL
Proof Work
Software-validated
SDK
Software Path
Public repo
FPGA
Prototype Paths
Evidence-labeled
SYNTH
Scaling Path
Zynq evidence-labeled

Founder

MR

Matt Rockwell

Inventor & Founder

Matt Rockwell is a systems engineer and founder of ATOMiK, with deep expertise in embedded systems, FPGA development, and formal verification. He created the delta-state algebra as a fundamental rethinking of how computers handle state — formalizing the core algebra before writing the first line of prototype code. ATOMiK grew from a mathematical insight into a hardware-validated computing architecture running through RISC-V FPGA prototype paths.

Designed the delta-state algebra, wrote the formal proofs, built the hardware, and published the software tooling. ATOMiK is a solo-founder deep-tech company — the public proof, SDK, and prototype work trace back to one engineer building a sharper primitive for state-heavy systems.

Why ATOMiK?

ATOMiK began with a simple question: what if we never needed to copy state at all?

Traditional computing wastes enormous resources moving data that hasn't changed. Delta-state algebra addresses this by design — tracking only what changes, with formal proof work around the core algebra.

From formal proof work to RISC-V FPGA prototypes, ATOMiK is the result of building from first principles and labeling evidence boundaries explicitly.

What Comes Next

From FPGA validation to custom silicon exploration. See the evidence-labeled roadmap.

View ASIC Roadmap