ASIC Roadmap

From FPGA to Custom Silicon

ATOMiK's delta-state algebra has formal proof work, FPGA validation artifacts, and a synthesis-characterized path toward first silicon.

Formal Proof

Software

Evidence-labeled

Peak FPGA

Synthesis

Zynq XC7Z020, N=512

Single Core

Synthesis

See evidence labels

First Silicon

Roadmap

Not measured ASIC

Synthesis Scaling

Zynq rows are synthesis-characterized and should be quoted only from source artifacts. ASIC rows are roadmap projections until silicon exists and is measured.

Zynq low-bank
Synthesis row · source · artifact
Zynq mid-bank
Synthesis row · source · artifact
Zynq high-bank
Synthesis ceiling · source · artifact
ASIC path
Roadmap · projected · projected

Development Timeline

Each phase is separated by evidence status so synthesis, hardware validation, and roadmap work do not blur together.

✓
Phase 0Evidence

Mathematical Foundation

  • ▸Formal proof work for delta-state algebra properties
  • ▸Abelian group: commutative, associative, self-inverse, identity
  • ▸Security and timing claims require a specific threat model and measured boundary
Software-validated proof work
✓
Phase 1Evidence

Gowin FPGA — Tang Nano 9K

  • ▸Custom RV64I CPU + ATOMiK ISA extensions on GW1NR-9K
  • ▸HDMI output and display pipeline prototype work
  • ▸Multi-node delta streaming prototype path
  • ▸Exact compliance, timing, and display-test counts belong in source artifacts
FPGA prototype path
✓
Phase 2Evidence

Xilinx Zynq XC7Z020 — Parallel Scaling + Linux

  • ▸Synthesis-characterized scaling path on XC7Z020
  • ▸Linux userspace validation path documented through /dev/mem and MMIO ordering
  • ▸Live AX7020/Zynq prototype work is tracked separately from synthesis ceilings
  • ▸Exact counts and frequencies should be quoted only from source artifacts
Synthesis + hardware-validation evidence
4
Phase 3In Progress

Sky130 Trial Tape-out

  • ▸Open-source PDK via Efabless / Silicon Catalyst partnership
  • ▸Gate-count and area estimates remain projected until tape-out artifacts exist
  • ▸Prepare a first-silicon evaluation chip path
  • ▸Full open-source toolchain: OpenLane 2, Magic, KLayout
First-silicon evaluation path
5
Phase 4Planned

Foundry / IP Partnership

  • ▸TSMC / Samsung / GlobalFoundries engagement
  • ▸SRAM compiler integration for on-die state tables
  • ▸Multi-bank ASIC with dedicated on-die interconnect
  • ▸Projected custom-silicon target with die area and throughput to be validated
6
Phase 5Planned

Volume ASIC — Edge + Data-Center SKUs

  • ▸Edge SKU concept for IoT / embedded evaluation
  • ▸Data-center SKU: thousands of parallel banks, PCIe / CXL attach
  • ▸Hardware root-of-trust direction with timing claims held for evidence
  • ▸Power and throughput improvements remain projected until measured silicon exists

Interested in ATOMiK Silicon?

ATOMiK is preparing the path toward a first-silicon evaluation chip. Get in touch to discuss design-partner fit, licensing, or technical diligence.

Discuss Licensing

Use the evaluation form to anchor on workload, proof boundary, and timeline.

Questions about our timeline? Contact us