ASIC Roadmap

From FPGA to Custom Silicon

ATOMiK's delta-state algebra is formally verified, FPGA-validated at 69.7 Gops/s, and on a clear path to >1 Tops/s in ASIC with minimal die area.

Lean 4 Proofs

92

Theorems verified

Peak FPGA

69.7 Gops/s

Zynq XC7Z020, N=512

Single Core

444 MHz

302 LUT, 446 Mops/s

ASIC Target

>1 Tops/s

>1 GHz, ~25K gates

Throughput Scaling

Sub-linear resource growth: 3.7× LUT increase yields 16× throughput. ASIC projections assume >1 GHz clock with equivalent bank count.

N=1
446 Mops/s · 444 MHz · 302 LUT
N=16
4.4 Gops/s · 267 MHz · 941 LUT
N=512
69.7 Gops/s · 136 MHz · 23,542 LUT
ASIC (proj.)
>1 Tops/s · >1 GHz · ~25K gates LUT

Development Timeline

Each phase builds on hardware-validated results from the previous one — no paper designs.

✓
Phase 0Validated

Mathematical Foundation

  • ▸92 Lean 4 theorems proving delta-state algebra properties
  • ▸Abelian group: commutative, associative, self-inverse, identity
  • ▸Security architecture: no caches, no speculation, deterministic latency
Formally verified correctness
✓
Phase 1Validated

Gowin FPGA — Tang Nano 9K

  • ▸Custom RV64I CPU + ATOMiK ISA extensions on GW1NR-9K
  • ▸1280×720 @60 Hz HDMI output from a $13.50 FPGA
  • ▸Multi-node delta streaming: dual-SoC convergence proven
  • ▸53/54 compliance, 9/9 ATOMiK, 10/10 integration, 6/6 display tests
Production firmware running today
✓
Phase 2Validated

Xilinx Zynq XC7Z020 — Parallel Scaling

  • ▸N=1 single bank: 302 LUT, 444 MHz, 446 Mops/s
  • ▸N=16 parallel banks: 941 LUT, 267 MHz, 4.4 Gops/s
  • ▸N=512 peak config: 23,542 LUT, 136 MHz, 69.7 Gops/s
  • ▸Sub-linear scaling: 3.7× LUT growth for 16× throughput
69.7 Gops/s on a $99 FPGA
4
Phase 3In Progress

Sky130 Trial Tape-out

  • ▸Open-source PDK via Efabless / Silicon Catalyst partnership
  • ▸Gate-count estimate: ~500 gates for a single ATOMiK core
  • ▸Prove delta-state algebra works in custom silicon
  • ▸Full open-source toolchain: OpenLane 2, Magic, KLayout
First silicon target
5
Phase 4Planned

Production Foundry Partnership

  • ▸TSMC / Samsung / GlobalFoundries engagement
  • ▸SRAM compiler integration for on-die state tables
  • ▸Multi-bank ASIC with dedicated on-die interconnect
  • ▸Target: >1 GHz clock, >1 Tops/s with minimal die area
6
Phase 5Planned

Volume ASIC — Edge + Data-Center SKUs

  • ▸Edge SKU: ultra-low-power, sub-1 mm² die for IoT / embedded
  • ▸Data-center SKU: thousands of parallel banks, PCIe / CXL attach
  • ▸Hardware root-of-trust with zero timing side channels
  • ▸Orders-of-magnitude improvement over FPGA on power and throughput

Interested in ATOMiK Silicon?

We're partnering with foundries and system integrators to bring formally verified delta-state processing to custom silicon. Get in touch to discuss early access, licensing, or integration.

Contact Sales

sales@atomik.tech